Method for trimming non-volatile memory cells

ABSTRACT

A method for trimming a non-volatile memory cell. One method comprising, erasing the memory cell below a desired voltage threshold (Vt) level, applying a program pulse to the memory cell, reading the memory cell, comparing a current conducted by the memory cell with an externally provided reference current using a sense amplifier that is internal to a memory device that contains the memory cell, producing a digital output based on the comparison of the currents and applying successive program pulses until the digital output changes from one logic state to another.

RELATED APPLICATION

[0001] This is a divisional application of U.S. patent application Ser.No. 09/818,957 filed Mar. 27, 2001, titled “Method and Apparatus ForTrimming Non-Volatile Memory Cells” and commonly assigned, the entirecontents of which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to non-volatile memoriesand in particular the present invention relates to trimming non-volatilereference memory cells.

BACKGROUND OF THE INVENTION

[0003] Memory devices are typically provided as internal storage areasin the computer. There are several different types of memory. One typeof memory is random access memory (RAM) that is typically used as mainmemory in a computer environment. Most RAM is volatile, which means thatit requires a steady flow of electricity to maintain its contents.Computers often contain a small amount of read-only memory (ROM) thatholds instructions for starting up the computer. An EEPROM (electricallyerasable programmable read-only memory) is a special type non-volatileROM that can be erased by exposing it to an electrical charge. Likeother types of ROM, EEPROM is traditionally not as fast as RAM. EEPROMcomprise a large number of memory cells having electrically isolatedgates (floating gates). Data is stored in the memory cells in the formof charge on the floating gates. Charge is transported to or removedfrom the floating gates by programming and erase operations,respectively.

[0004] Yet another type of non-volatile memory is a Flash memory. AFlash memory is a type of EEPROM that can be erased and reprogrammed inblocks instead of one byte at a time. A typical Flash memory comprises amemory array that includes a large number of memory cells arranged in arow and column fashion. Each memory cell includes a floating gatefield-effect transistor capable of holding a charge. The cells areusually grouped into erasable blocks. Each of the memory cells can beelectrically programmed in a random basis by charging the floating gate.The charge can be removed from the floating gate by an erase operation.Thus, the data in a cell is determined by the presence or absence of thecharge in the floating gate.

[0005] To program a memory cell, a high positive voltage Vg is appliedto the control gate of the cell. In addition, a moderate positivevoltage is applied to the drain (Vd) and the source voltage (Vs) and thesubstrate voltage (Vsub) are at ground level. These conditions result inthe inducement of hot electron injection in the channel region near thedrain region of the memory cell. These high-energy electrons travelthrough the thin gate oxide towards the positive voltage present on thecontrol gate and collect on the floating gate. The electrons remain onthe floating gate and function to reduce the effective threshold voltageof the cell as compared to a cell that has not been programmed. Aprogrammed non-volatile memory cell is said to be at a logic level of“0”.

[0006] In flash memories, blocks of memory cells are erased in groups.This is achieved by putting a negative voltage on the word lines of anentire block and coupling the source connection of the entire block toVcc (power supply), or higher. This creates a field that removeselectrons from the floating gates of the memory elements. In an erasedstate, the memory cells can be activated using a lower control gatevoltage. An erased non-volatile memory cell is said to be at a logiclevel of “1”.

[0007] Non-volatile memory systems, including flash memory systems, usea variety of sense amplifiers to verify the state of memory cells in amemory array. Verification of a non-volatile memory cell is accomplishedby applying a potential to the control gate of the cell to be verifiedand then using a sense amplifier to compare a current generated by thecell with a known current from a reference cell. The reference cell is anon-volatile memory cell or bit that has a predefined charge that is setor trimmed by the manufacture of the memory to produce a specificreference current in response to a known gate voltage. The senseamplifier determines whether the memory cell to be verified draws moreor less current than the reference current. By doing this, the senseamplifier determines if the memory cell is in a programmed state or anerased state.

[0008] The reference cell or cells are pre-programmed by the memorymanufactures. The time needed to program these cells to a desiredvoltage threshold (Vt) can be significant. Moreover, the longer it takesto program the cells the less memory devices can be produced for sale.Therefore, the longer the period of time needed to program referencecells, the more the memory device costs to make.

[0009] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foran improved method of preprogramming reference cells.

SUMMARY OF THE INVENTION

[0010] The above-mentioned problems with non-volatile memory devices andother problems are addressed by the present invention and will beunderstood by reading and studying the following specification.

[0011] In one embodiment, a method of trimming a non-volatile memorycell is disclosed. The method comprising, erasing the memory cell belowa desired voltage threshold (Vt) level. Applying a program pulse to thememory cell. Reading the memory cell. Comparing a current conducted bythe memory cell with an externally provided reference current, using asense amplifier that is internal to a memory device that contains thememory cell. Producing a digital output based on the comparison of thecurrents and applying successive program pulses until the digital outputchanges from one logic state to another

[0012] In another embodiment, a method of trimming a flash memory cellin a memory device with an external reference program tester isdisclosed. The method comprises erasing the flash memory cell below adesired voltage threshold (Vt) level. Programming the flash memory cellwith a programming pulse. Reading the flash memory cell, wherein theflash memory cell outputs a bit line current in response to the readingof the flash memory cell. Comparing the bit line current with areference current from the external reference program tester, whereinthe reference current is in relation to the desired Vt level. When thebit line current exceeds the reference current, verifying that the flashmemory cell has been successfully trimmed.

[0013] In yet another embodiment, a method of trimming a non-volatilememory cell in a memory device is disclosed. The method compriseserasing the nonvolatile memory cell below a select voltage threshold(Vt) level. Applying a program pulse to the non-volatile memory cell tocharge up the non-volatile memory cell. Reading the non-volatile memorycell. Coupling a bit line current from an output of the non-volatilecell to a first input of a sense amplifier, wherein the sense amplifieris internal to the memory device. Coupling an external reference currentto a second input of the sense amplifier, wherein the external referencecurrent is associated with the Vt level. Verifying the logic level of anoutput of the sense amplifier and determining if the non-volatile memorycell is properly trimmed based on the logic level of the output of thesense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a flow chart illustrating the pre-programming of areference cell of the prior art.

[0015]FIG. 2 is a block diagram of a memory device of an embodiment ofthe present invention.

[0016]FIG. 3 is a flow chart illustrating the pre-programming of areference cell of one embodiment the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings, which forma part hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present invention. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the claims.

[0018] The present invention reduces the test time required to trimreference cells to a specific threshold voltage by shortening a verifystep with the use of internal sense amplifiers in a memory device. Tobetter understand the present invention, further background is firstprovided.

[0019] Referring to FIG. 1, a flow chart of a traditional method oftrimming a reference cell (200) is illustrated. A reference cell istrimmed by first erasing the reference cell below the desired Vt (202).A program pulse is then applied to the reference bit or cell (204) tostore charge on the cell. A bitline access mode is then applied to thereference cell. The bitline access mode is a test mode that places avoltage, i.e. 1 volt, on the drain of the reference cell (206) and avoltage on the control gate of the reference cell (208). A testerportable memory unit (pmu) is then used to measure the current andverify if a reference cell (210) has reached the desired Vt. If thetarget Vt has not been reached on the reference cell, another programpulse is applied to the reference cell (204). Once again, a voltage isthen applied to the drain of the reference cell (206) and to the controlgate of the reference cell (208). The tester pmu once again measures thecurrent and verifies if the reference cell (210) has reached the Vt.This process is repeated until it is verified that a sufficient chargehas been stored on the floating gate of the reference cell.

[0020] The time required to verify a reference cell with a tester pmutakes a long period of time relative to the time needed to program thereference cell. Activating the tester pmu, to measure the current of thereference cell, can take up to 100 ms. Moreover, it can take seconds tocomplete verification if repeated cycles of applying program pulses tothe reference cell and measuring for Vt is required. Although a testerpmu or reference program tester is used in the present invention, abitline access mode is not used to measure the current of the referencecell to verify VT, thus no test time is wasted on tester pmu activationfor each verify cycle.

[0021] Referring to FIG. 2, one embodiment of the present invention isillustrated. FIG. 2 is a simplified illustration of the relevantelements of the present invention. As shown, a reference program testeror external tester equipment 102 is coupled to a memory device 100 tosupply a reference current to an input of sense amplifier 108 in acircuit of sense amplifiers 110. The reference program tester 102 has aninput 134 that is coupled to the output of the sense amplifier 108 toverify an output signal of the sense amplifier 108. Although, FIG. 2illustrates the reference program tester 102 being directly coupled tothe output of the sense amplifier 108, it will be understood in the artthat other elements of a non-volatile memory device (i.e. I/O buffer, ordata lines) may be coupled between the test circuit and the output ofthe sense amplifier and that the present invention is not limited to adirect connection of the reference program tester 102 to the senseamplifier 108.

[0022] The reference program tester 102 further has a command output(s)132 that is coupled to control circuitry 118 of the memory device 100 toprovide external commands to the control circuitry 118. The controlcircuitry 118 controls erase, program and other memory operations of thememory device 100. A high voltage switch/pump 116 is also shown toprovide a voltage source for the program pulses applied to the memorycells. A reference cell or reference memory cell 106 is illustrated inthe memory array 104. A drain of the reference cell 106 is coupled toanother input of the sense amplifier 108 by a bitline 120. The memorydevice 100 is further shown as having a column decode circuit 112 and arow decode circuit 114. Although, FIG. 2 is shown as only having onereference cell, it will be understood in the art that a memory devicemay have more than one reference cell and that the present invention isnot limited to one reference cell. Further, the reference cells may belocated in a separate “mini” array and not located with the primary dataarray.

[0023] Referring to FIG. 3, a flow chart of a method of trimming areference cell (300) of the present invention is illustrated. Thereference cell 106 is first erased below a desired Vt (302) by thecontrol circuitry 118. A reference current output 130 of the referenceprogram tester 102 then supplies a reference current to an input ofsense amplifier 108. The reference current level is equal to a currentlevel that would be indicative of a current supplied by an accessedmemory cell having the desired Vt. The reference current is supplied tothe sense amplifier 108 during the remainder of the trimming cycle. Alow level program pulse is then applied to the control gate of thereference cell 106 (306) to gently charge up the reference cell 106. Thelow level program pulse is used to add a small charge to the referencecell. In one embodiment, the low level program pulse includes applyingapproximately 8 volts to the control gate of the reference cell andapproximately 5.4 volts to the drain of the reference cell while thesource and the substrate of the reference cell is at ground level. Thislow level program pulse is applied for a period of approximately 1 ms.The reference cell 106 is then read (308). As known to those in the art,a cell is read by providing a predetermined access voltage to a wordlinecoupled to a control gate of the cell. For, example, in one embodiment,an access voltage of approximately 3.9 volts is used. In anotherembodiment, an access voltage of approximately 3.4 volts is used. Inresponse to the access voltage, the cell provides a cell or bit currentin a bitline that is coupled to a drain of the cell. The cell or bitcurrent in the bitline is indicative of the charge stored on the cell orbit.

[0024] Reading or accessing the reference cell provides a cell currentfrom the reference cell 106 to the other input of the sense amplifier108. The sense amplifier 108 then compares the cell current supplied bythe reference cell 106 to the reference current supplied by thereference program tester 102 (310). The sense amplifier outputs a logiclevel of a “1” or a logic level of a “0”. In one embodiment of thepresent invention, an output of a logic level 1 indicates the referencecell is below the desired Vt and that an additional program pulse isneeded and an output of a logic level 0 indicates the reference cellexceeds the desired Vt. In this embodiment, when the output transitionsfrom a logic level 1 to a logic level 0, the trimming cycle is complete.In another embodiment of the present invention, an output of a logiclevel 0 indicates the reference cell is below the desired Vt and that anadditional program pulse is needed and an output of a logic level 1indicates the reference cell exceeds the desired Vt. In this embodiment,when the output transitions from a logic level 0 to a logic level 1, thetrimming cycle is complete. Verifying with the use of internal senseamplifiers of a memory device can be done in approximately 200 ns percycle. That is, it only takes about 200 ns to verify the state of areference cell after a program pulse has been applied.

[0025] Unlike the prior art method of verifying a reference cell, thepresent invention does not directly measure the reference current butmonitors the logic output of the memory device containing the referencecell. That is, the present invention verifies a reference cell when thereference cell transitions from a memory cell having a voltage levelbelow the desired Vt to a memory cell having a voltage level above thedesired Vt as indicated by the logic output. The resulting voltage levelon the reference cell provides a current that is above the referencecurrent. The difference in the resulting voltage level on the referencecell is determined by the strength of the program pulse applied. Thatis, the lower the strength of the program pulse, the less charge will bestored on the floating gate of the memory cell and the closer thevoltage level of the reference memory cell will be to the desired Vtlevel once the logic output changes. A longer programming pulse willprogram the reference cell with less programming pulses, but shorterprogramming pulses provide for a more accurate trim.

CONCLUSION

[0026] A method and apparatus for trimming a non-volatile memory cellhas been disclosed. One method comprising, erasing the memory cell belowa desired voltage threshold (Vt) level, applying a program pulse to thememory cell, reading the memory cell, comparing a current conducted bythe memory cell with an externally provided reference current using asense amplifier that is internal to a memory device that contains thememory cell, producing a digital output based on the comparison of thecurrents and applying successive program pulses until the digital outputchanges from one logic state to another.

[0027] Although specific methods and embodiments have been illustratedand described herein, it will be appreciated by those of ordinary skillin the art that any arrangement, which is calculated to achieve the samepurpose, may be substituted for the specific embodiment shown. Thisapplication is intended to cover any adaptations or variations of thepresent invention. Therefore, it is manifestly intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A method of trimming a non-volatile memory cellcomprising: erasing the memory cell below a desired voltage threshold(Vt) level; applying a program pulse to the memory cell; reading thememory cell; comparing a current conducted by the memory cell with anexternally provided reference current using a sense amplifier that isinternal to a memory device that contains the memory cell; producing adigital output based on the comparison of the currents; and applyingsuccessive program pulses until the digital output changes from onelogic state to another.
 2. The method of claim 1 wherein a digitaloutput of a logic level 1 indicates the memory cell has voltage levelbelow the desired Vt, further wherein the successive program pulses areapplied until the digital output changes from the logic level 1 to alogic level
 0. 3. The method of claim 1 wherein a digital output of alogic level 0 indicates the memory cell has voltage level below thedesired Vt, further wherein the successive program pulses are applieduntil the digital output changes from the logic level 0 to a logiclevel
 1. 4. The method of claim 1 wherein the program pulse is a lowlevel program pulse to gently charge up the memory cell.
 5. The methodof claim 4 wherein the low level program pulse is a program pulsewherein the program pulse further comprises; applying approximately 8volts to a control gate of the memory cell for approximately 1 ms; andapplying approximately 5.4 volts to a drain of the memory cellconcurrently with the 8 volts being applied to the control gate of thememory cell while a source and a substrate of the memory cell are atground.
 6. The method of claim 1 wherein reading the memory cell furthercomprises applying a predetermined access voltage to a control gate ofthe memory cell.
 7. The method of claim 6 wherein the predeterminedaccess voltage is approximately 3.9 volts.
 8. The method of claim 6wherein the predetermined access voltage is approximately 3.5 volts. 9.A method of trimming a flash memory cell in a memory device with anexternal reference program tester, the method comprising: erasing theflash memory cell below a desired voltage threshold (Vt) level;programming the flash memory cell with a programming pulse; reading theflash memory cell, wherein the flash memory cell outputs a bit linecurrent in response to the reading of the flash memory cell; comparingthe bit line current with a reference current from the externalreference program tester, wherein the reference current is in relationto the desired Vt level; and when the bit line current exceeds thereference current, verifying that the flash memory cell has beensuccessfully trimmed.
 10. The method of claim 9, further comprising:when the bit line current is less than the reference current, applyinganother programming pulse to the flash memory cell.
 11. The method ofclaim 9, further comprising: outputting a first logic state when the bitline current is less than the reference current and a second logic statewhen the bit line current is more than the reference current.
 12. Themethod of claim 9, further comprising: coupling command signals from theexternal reference program tester to control circuitry in the memorydevice, wherein the command signals direct the control circuitry toperform trimming procedures.
 13. The method of claim 9, whereincomparing the bit line current with the reference current furthercomprises: coupling the bit line current to a first input of senseamplifier; coupling the reference current to a second input of the senseamplifier; and reading the logic state of an output of the senseamplifier.
 14. The method of claim 13, wherein the sense amplifier isinternal to the memory device.
 15. A method of trimming a non-volatilememory cell in a memory device, the method comprising: erasing thenon-volatile memory cell below a select voltage threshold (Vt) level;applying a program pulse to the non-volatile memory cell to charge upthe nonvolatile memory cell; reading the non-volatile memory cell;coupling a bit line current from an output of the non-volatile cell to afirst input of a sense amplifier, wherein the sense amplifier isinternal to the memory device; coupling an external reference current toa second input of the sense amplifier, wherein the external referencecurrent is associated with the Vt level; verifying the logic level of anoutput of the sense amplifier; and determining if the non-volatilememory cell is properly trimmed based on the logic level of the outputof the sense amplifier.
 16. The method of claim 15, wherein the externalreference current is supplied by external tester equipment.
 17. Themethod of claim 15, further comprising: coupling external commands fromexternal tester equipment to control circuitry in the memory device,wherein the external commands direct the control circuitry to trim thenon-volatile memory cell.
 18. The method of claim 15, wherein verifyingthe logic level of the output of the sense amplifier further comprises:coupling external tester equipment to the output of the sense amplifierto read the logic level of the output of the sense amplifier.
 19. Themethod of claim 15, further comprising: when the non-volatile memorycell is determined not to be properly trimmed, applying another programpulse.
 20. The method of claim 15, wherein the program pulse isrelatively a low level program pulse to gently charge up thenon-volatile memory cell.